x_heep_gen.system module
- class x_heep_gen.system.BusType(value, names=None, *, module=None, qualname=None, type=None, start=1, boundary=None)
Bases:
EnumEnumeration of all supported bus types
- NtoM = 'NtoM'
- onetoM = 'onetoM'
- class x_heep_gen.system.Override(bus_type: BusType | None, numbanks: int | None, numbanks_il: int | None)
Bases:
objectBundles information that can be overriden in the XHeep class.
- class x_heep_gen.system.XHeep(bus_type: BusType, ram_start_address: int = 0, override: Override | None = None)
Bases:
objectThis object represents the whole mcu.
An instance of this object is also passed to the mako templates.
- Parameters:
- Raises:
TypeError – when parameters are of incorrect type.
- IL_COMPATIBLE_BUS_TYPES: Set[BusType] = {BusType.NtoM}
Constant set of bus types that support interleaved memory banks
- add_linker_section(section: LinkerSection)
Function to add a linker section. :param LinkerSection section: Linker section to add. :param str name: the name of the section. :raise ValueError: if the name was allready used for another section or the first and second are not code and data.
- add_linker_section_for_banks(banks: List[Bank], name: str)
Function to add linker sections coupled to some banks. :param List[Bank] banks: list of banks that compose the section, assumed to be continuous in memory :param str name: the name of the section. :raise ValueError: if the name was allready used for another section or the first and second are not code and data.
- add_ram_banks(bank_sizes: List[int], section_name: str = '')
Add ram banks in continuous address mode to the system. The bank size should be a power of two and at least 1kiB.
- Parameters:
- Raises:
TypeError – when arguments are of wrong type
ValueError – when banks have an incorrect size.
ValueError – if the name was allready used for another section or the first and second are not code and data.
ValueError – if bank_sizes list is empty
- add_ram_banks_il(num: int, bank_size: int, section_name: str = '', ignore_ignore: bool = False)
Add ram banks in interleaved mode to the system. The bank size should be a power of two and at least 1kiB, the number of banks should also be a power of two.
- Parameters:
num (int) – number of banks to add
bank_size (int) – size of the banks in kiB
section_name (str) – If not empty adds automatically a linker section for this banks. The names must be unique and not be used by the linker for other purposes.
ignore_ignore (bool) – Ignores the fact that an override was set. For internal uses to apply this override.
- Raises:
TypeError – when arguments are of wrong type
ValueError – when banks have an incorrect size or their number is not a power of two.
ValueError – if the name was allready used for another section or the first and second are not code and data.
- build()
Makes the system ready to be used.
Aplies the overrides for the interleaved memory as the normal memory needs to be configured first.
Sorts the linker sections by starting address.
Inferes the missing linker section ends with the start of the next section if present. If not it uses the end of the last memory bank.
- iter_bank_numwords() Generator[int, None, None]
Iterates over the size of the ram banks in number of words.
- Returns:
Generator over the sizes
- Return type:
Generator[int, None, None]
- iter_cont_ram_banks() Iterable[Bank]
- Returns:
an iterator over all continuous banks.
- Return type:
Iterable[Bank]
- iter_il_groups() Iterable[ILRamGroup]
- Returns:
an iterator over the interleaved ram bank groups.
- Return type:
Iterable[ILRamGroup]
- iter_il_ram_banks() Iterable[Bank]
- Returns:
an iterator over all interleaved banks.
- Return type:
Iterable[Bank]
- iter_linker_sections() Iterable[LinkerSection]
- Returns:
an iterator over the linker sections
- Return type:
Iterable[LinkerSection]