xheep_gen.cpu.cv32e20 module

class xheep_gen.cpu.cv32e20.cv32e20(rv32e=None, rv32m=None)

Bases: CPU

Represents the CV32E20 CPU configuration with optional parameters.

RV32M_MODES = {'RV32MFast', 'RV32MNone', 'RV32MSingleCycle', 'RV32MSlow'}

get_sv_str(param_name: str) → str

Get the string representation of the param_name parameter to be used in the SystemVerilog templates. :param param_name: Name of the parameter. :return: String representation of the parameter for SystemVerilog or an empty string if not defined.