xheep_gen.cpu.cv32e40p module

class xheep_gen.cpu.cv32e40p.cv32e40p(fpu=None, fpu_addmul_lat=None, fpu_others_lat=None, zfinx=None, corev_pulp=None, num_mhpmcounters=None)

Bases: CPU

Represents the CV32E40P CPU configuration with optional parameters.

get_sv_str(param_name: str) → str

Get the string representation of the param_name parameter to be used in the SystemVerilog templates. :param param_name: Name of the parameter. :return: String representation of the parameter for SystemVerilog or an empty string if not defined.