X-HEEP Logo
  • Getting started
  • How to…
  • Configuration
    • System Configuration
    • CPU Configuration
    • CORE-V eXtension Interface (CV-X-IF) Configuration
    • Memory Banks Configuration
    • Bus Type Configuration
    • Linker Configuration
    • Pad Configuration
    • Peripheral Configuration
    • Extension Configuration
    • xheep_gen
      • xheep_gen package
        • Subpackages
        • Submodules
        • Module contents
  • eXtending X-HEEP
  • Testing
  • Peripherals
  • External Peripherals
  • FPGA
  • ASICs
X-HEEP
  • Configuration
  • xheep_gen
  • xheep_gen package
  • xheep_gen.peripherals package
  • xheep_gen.peripherals.user_peripherals package
  • View page source

xheep_gen.peripherals.user_peripherals package

Submodules

  • xheep_gen.peripherals.user_peripherals.GPIO module
    • GPIO
  • xheep_gen.peripherals.user_peripherals.I2C module
    • I2C
  • xheep_gen.peripherals.user_peripherals.I2S module
    • I2S
  • xheep_gen.peripherals.user_peripherals.PDM2PCM module
    • PDM2PCM
      • PDM2PCM.get_cic_mode()
  • xheep_gen.peripherals.user_peripherals.RV_plic module
    • RV_plic
  • xheep_gen.peripherals.user_peripherals.RV_timer module
    • RV_timer
  • xheep_gen.peripherals.user_peripherals.SPI2 module
    • SPI2
  • xheep_gen.peripherals.user_peripherals.SPI_host module
    • SPI_host
  • xheep_gen.peripherals.user_peripherals.UART module
    • UART
  • xheep_gen.peripherals.user_peripherals.serial_link module
    • SerialLink
  • xheep_gen.peripherals.user_peripherals.serial_link_receiver_fifo module
    • SerialLinkReceiverFifo
  • xheep_gen.peripherals.user_peripherals.serial_link_reg module
    • SerialLinkReg

Module contents

Previous Next

© Copyright 2025, EPFL.

Built with Sphinx using a theme provided by Read the Docs.